1. Field of the Invention
The present invention relates to a pillar-shaped semiconductor device and a production method therefor.
2. Description of the Related Art
Surrounding gate MOS transistors (SGTs), which are representative examples of pillar-shaped semiconductor devices, have drawn much attention in recent years as semiconductor elements that offer highly integrated semiconductor devices. However, SGT-including semiconductor devices that achieve higher degrees of integration are in demand.
In a typical planar-type MOS transistor, a channel lies in a horizontal direction along the upper surface of a semiconductor substrate. In contrast, a channel of an SGT lies in a direction perpendicular to the upper surface of a semiconductor substrate (for example, refer to Japanese Unexamined Patent Application Publication No. 2-188966 and Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol. 38, No. 3, pp. 573-578 (1991)). Accordingly, the density of semiconductor devices can be increased by using SGTs instead of planar-type MOS transistors.
FIG. 7 is a schematic diagram of an N-channel SGT. N+ regions 101a and 101 b (a semiconductor region having a high donor impurity concentration is referred to as an “N+ region” hereinafter), which respectively serve as a source and a drain or vice versa, are respectively formed in a lower portion and an upper portion of a Si pillar 100 (a silicon semiconductor pillar is referred to as a “Si pillar” hereinafter) whose conductivity type is P-type or i-type (intrinsic). The portion of the Si pillar 100 sandwiched by the N+ regions 101a and 101b serving as a source and a drain serves as a channel region 102. A gate insulating layer 103 surrounds the channel region 102, and a gate conductor layer 104 surrounds the gate insulating layer 103. In an SGT, the N+ regions 101a and 101b serving as a source and a drain, the channel region 102, the gate insulating layer 103, and the gate conductor layer 104 are formed within a single Si pillar 100. Accordingly, the area of the SGT in a plan view is equal to the area of one source or drain N+ region of a planar-type MOS transistor. Thus, circuit chips having SGTs achieve further size reduction compared to circuit chips having planar-type MOS transistors.
For example, as illustrated in the schematic diagram of FIG. 8, it is anticipated that the circuit area can be decreased by forming two SGTs 116a and 116b in lower and upper portions of one Si pillar 115.
FIG. 8 is a schematic diagram of a circuit in which an N-channel SGT 116a is formed in a lower portion of the Si pillar 115, and a P-channel SGT 116b is formed above the N-channel SGT 116a. The Si pillar 115 is formed on a P-layer substrate 117 (a semiconductor layer containing an acceptor impurity is referred to as a “P-layer” hereinafter). A SiO2 layer 118 is formed on the P-layer substrate 117 in a peripheral region surrounding the Si pillar 115. A gate insulating layer 119a of the N-channel SGT 116a and a gate insulating layer 119b of the P-channel SGT 116b surround the Si pillar 115. A gate conductor layer 120a of the N-channel SGT 116a and a gate conductor layer 120b of the P-channel SGT 116b are formed along the outer periphery of the Si pillar 115 so as to surround the gate insulating layers 119a and 119b. An N+ region 121a is formed in a surface layer portion of the P-layer substrate 117 connected to the bottom of the Si pillar 115. An N+ region 121b, a SiO2 layer 130 that lies on and is connected to the N+ region 121b, and a P+ region 122a (a semiconductor region having a high acceptor impurity concentration is referred to as a “P+ region” hereinafter) that lies on and is connected to the SiO2 layer 130 are formed in a middle portion of the Si pillar 115. A P+ region 122b is formed in a top portion of the Si pillar 115. The N+ region 121a serves as a source of the N-channel SGT 116a, and the N+ region 121b serves as a drain of the N-channel SGT 116a. The part of the Si pillar 115 sandwiched by the N+ region 121a and N+ region 121b is a channel region 123a of the N-channel SGT 116a. The P+ region 122b serves as a drain of the P-channel SGT 116b, and the P+ region 122a serves as a source of the P-channel SGT 116b. The part of the Si pillar 115 sandwiched between the P+ region 122a and the P+ region 122b is a channel region 123b of the P-channel SGT 116b. A nickel silicide layer (NiSi layer) 125a is formed in a surface layer portion of the N+ region 121a connected to the bottom of the Si pillar 115. In a central portion of the Si pillar 115, a NiSi layer 125b is formed along the outer periphery of the N+ region 121b and a NiSi layer 125c is formed along the outer periphery of the P+ region 122a. A NiSi layer 125d is formed in an upper surface layer of the P+ region 122b in the top portion of the Si pillar 115. A source wiring metal layer 126a is connected to the NiSi layer 125a in the N+ region 121a, and also to a VS1 terminal. A drain wiring metal layer 126b is connected to the NiSi layer 125b and also to a drain terminal VD1. A source wiring metal layer 126c is connected to the NiSi layer 125c in the P+ region 122a and also to a VS2 terminal. A drain wiring metal layer 126d is connected to the NiSi layer 125d and also to a VD2 terminal. Gate wiring metal layers 127a and 127b are connected to the gate conductor layer 120a and the gate conductor layer 120b, and also to gate terminals VG1 and VG2, respectively. According to this configuration, two SGTs 116a and 116b isolated by the SiO2 layer 130 are formed in the Si pillar 115.
As illustrated in FIG. 8, when two SGTs 116a and 116b isolated by the SiO2 layer 130 are formed in the Si pillar 115, the following issues arise.
1. It is difficult to accurately and easily form, in a middle portion of the Si pillar 115, an N+ region 121b and a P+ region 122a isolated by a SiO2 layer 130.
2. It is difficult to accurately and easily form a NiSi layer 125b and a NiSi layer 125c along the outer peripheries of the N+ region 121b and the P+ region 122a. 
3. It is difficult to accurately and easily establish connection between the NiSi layer 125b and the drain wiring metal layer 126b and between the NiSi layer 125c and the source wiring metal layer 126c. 
4. It is difficult to prevent bending or collapsing of the Si pillar 115 caused by the difference in linear thermal expansion coefficient between NiSi (12×10−6/K) and Si (2.4×10−6/K) in forming the NiSi layer 125b and the NiSi layer 125c in the Si pillar 115.